1. Field of the Invention
The present invention relates to circuit boards, and more particularly, to contacts on printed circuit boards.
2. Description of the Related Art
To meet the increase in signal transmission speeds of digital circuits having semiconductor-integrated circuit devices, a low-voltage interfacing technique has been developed, in which signals with a low voltage of 1V or less are transmitted.
In particular, as operating speeds of semiconductor integrated circuit devices increase, signals have sharper edges, i.e., the signal transition times decrease. Consequently, waveform distortion arises from unmatched impedance. To reduce waveform distortion, a matched termination method has been widely used, in which a bus is terminated with a line impedance.
FIG. 1 presents a schematic illustrating a general wiring scheme. The reference numeral 100 denotes a printed circuit board also referred to as a “circuit board”, “system board”, “backboard” or a “backplane”. The backboard 100 can include connectors or sockets 41 and 42 which connect modules 1 and 2 to a bus 10 connected to a control unit 110. The sockets 41 and 42 can be connected with each other via the bus 10. The bus 10 can be terminated with a termination resistor or a terminator Rtt 200 and a termination voltage Vtt 300 to provide a matched termination.
Modules 1 and 2 are representative functional circuit boards or memory modules that are capable of transmitting data to or receiving data from functional circuits disposed on the backboard 100 or memory devices 31 and 32 via the bus 10. The memory devices 31 and 32 can be connected to the bus 10 through wiring or stub buses 11 and 12.
In the general wiring scheme of FIG. 1, the line lengths of the stub buses 11 and 12 are at a length such that signals having high speed falling or rising transition times conducted thereon may exhibit negative characteristics. For example, an unmatched impedance on the stub bus may distort the waveforms conducted thereon.
FIGS. 2A through 2C illustrate representative waveforms of signals of the memory devices 31 and 32 according to the operating frequency of the wiring scheme of FIG. 1. Referring to FIG. 2A, in a situation where the operating frequency of the wiring scheme of FIG. 1 is, for example, 533 Mega bits per second (Mbps), the waveforms of signals of the memory devices 31 and 32 can be relatively stable. Referring to FIG. 2B, in a situation where the operating frequency of the circuit system of FIG. 1 is, for example, 667 Mbps, the waveforms of signals of the memory devices 31 and 32 can be skewed and/or distorted. Referring to FIG. 2C, in a situation where the operating frequency of the circuit system of FIG. 1 is, for example, 800 Mbps, the waveforms of signals of the memory devices 31 and 32 can be severely distorted.
Accordingly, central processing unit (CPU) performance improvement may require memory performance improvement. Memory devices, for example, double data rate synchronous dynamic Random Access Memory (DDR SDRAMs) generally have the operating frequency of about 533 Mbps or about 667 Mbps. Thus, the wiring scheme of FIG. 1 can prevent distortion. However, it is difficult to implement a next-generation dynamic Random Access Memory (DRAM) with the operating frequency of at least about 800 Mpbs or about 1333 Mbps using the general wiring scheme of FIG. 1, i.e., a stub bus interface.